Conventional approaches to modeling and simulating bitcell operations rely on electronic circuit simulators such as SPICE models. Top-level simulations of such operations for large bitcell arrays (e.g., EEPROM) include multiple cycles of erase and/or program operations. However, conventional simulation techniques lack the ability to modify the threshold voltage during transition of a bitcell from one state to another. As a result, the logic value of the bitcell cannot be switched between “1” and “0” without generating simulation errors. Specifically, the simulation fails because a verify operation after the erase or program operation reports either a failed or passed status depending on an expected bit value. In addition, conventional bitcell simulators (e.g., SPICE) are slow because of the large number of simulation parameters involved. Due to these disadvantages, top-level simulations of memory arrays cannot complete a complete erase or program cycle accurately and without operator guidance.
A need therefore exists for methodology enabling full-cycle top-level simulation of large programmable bitcell arrays by utilizing transitional bitcell models.